Flash memories may be configured as NOR flash memories or as NAND flash memories. In a NOR flash memory, the memory cells are connected to the bitlines in parallel so that if any memory cell is turned on by the corresponding wordline, the bitline goes low. In a NAND flash memory, a number of transistors are connected in series so that a NAND flash memory structure may provide a higher density of memory cells than may be provided in a NOR flash memory. Moreover. NAND flash memories may provide faster programming and erasing times than may be provided by NOR flash memories.
NAND flash memory structures are discussed, for example, in U.S. Pat. No. 5,473,563 to Suh et al. entitled “Nonvolatile Semiconductor Memory” and assigned to the assignee of the present application. As discussed in the '563 Suh patent, a NAND structured flash memory may include a first selection transistor with a drain connected to a corresponding bitline via a contact hole, a second selection transistor with a source connected to a common source line, and eight memory transistors with channels connected in series between a source of the first selection transistor and a drain of the second selection transistor. The first and second selection transistors and the eight memory transistors may be formed on a p-type semiconductor substrate, and each memory transistor may include a floating gate layer formed on a gate oxide layer over a channel region between its source and drain regions and a control gate layer separated from the floating gate layer by an intermediate insulating layer. To program or write a selected one of the memory transistors, an operation of simultaneously erasing all of the memory transistors may be followed by programming the selected memory transistor.
When programming a selected memory transistor, a program voltage may be applied to a selected wordline of a selected memory block (corresponding to the selected memory cell) and a pass voltage may be applied to unselected wordlines of the selected memory block (corresponding to unselected memory cells). Channel regions and source and drain junctions of memory transistors of cell units in the selected memory block may be charged to a program inhibition voltage. Channel regions and source and drain junctions of cell units associated with memory transistors programmed to the other binary data may be discharged to be programmed while those of cell units associated with nonprogrammed memory transistors may be maintained at the program inhibition voltage to prevent programming.
A flash memory device may include Single-Level Cell (SLC) transistors or Multi-Level Cell (MLC) transistors depending on a number of data bits stored in each memory cell transistor. One (1) bit of data having a logic value of “1” or “0” can be stored in an SLC transistor. Two (2) bits of data having a logic value of “11”, “10”, “01” or “00” can be stored in an MLC transistor. Therefore, flash memory devices including MLC transistors may provide more highly integrated semiconductor devices for increased capacity.
Incremental Step Pulse Programming (ISPP) has been developed to increase program speeds for flash memory devices including MLC transistors. With Incremental Step Pulse Programming, a threshold voltage of a selected MLC transistor is changed to a voltage corresponding to a data value to be stored (any one of “11”, “10” “01” and “00”).